1. Field of the Invention
The present invention relates to the design of circuitry within semiconductor chips. More specifically, the present invention relates to a method and an apparatus that uses chip lamination to operatively couple an integrated circuit with a microstrip transmission line.
2. Related Art
As integration densities on semiconductor chips continue to increase, wires on the semiconductor chips have become extremely thin and squat, and hence very resistive, making them poor communication channels over long distances. Signal propagation delays for these wires are largely determined by the product of their resistance and capacitance, and are far slower than the maximum speed of electromagnetic signals through silicon dioxide. Making a wire wider (though still squat) can improve the wire's latency somewhat, but at the expense of bandwidth, since wider wires consume more space than thinner ones. Hence, the technique of widening wires to achieve latency reduction provides diminishing returns as wires become very wide.
System architects and circuit designers are beginning to view these wire performance limitations as one of the most pressing technological problems that must be overcome in order to keep increasing computer system performance. Radio-frequency circuit designers, too, find the high resistivity of on-chip wires troubling. The high loss in these wires lowers the quality factor of on-chip resonators and antennae, and increases the loss in distributed circuits, making such designs expensive and inefficient.
By contrast, transmission lines, typically on printed circuit boards (PCBs), are not very resistive. Hence, signal propagation in these transmission lines is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). Consequently, these transmission lines can propagate signals rapidly across long distances. They can also act as high-quality resonators and low-loss distributed circuits.
Although transmission lines have desirable characteristics, good transmission lines cannot be built using conventional fabrication technologies for integrated circuits. Even when on-chip wires are constructed as wide traces and are isolated from other wires, their small thickness still causes a significant resistive loss. In addition, isolating such wire traces can consume significant metal resources.
Hence, what is needed is a method and an apparatus for using transmission lines to improve the performance of an integrated circuit without the above-described problems.